Avery Design Debuts CXL(TM) 2.0 System-level VIP Simulation Solution

Newsfile Corp.
·2 min read

Tewksbury, Massachusetts--(Newsfile Corp. - April 15, 2021) - Avery Design Systems, a leader in functional verification solutions, today announced its CXLTM 2.0 system-level simulation solution. The comprehensive offering supports the co-simulation of a CXL-aware Linux kernel and QEMU x86 virtual host system emulator with its SystemVerilog CXL Host VIP. The solution enables pre-silicon hardware-software validation of CXL 2.0 Type 3 memory expansion system designs, accelerating development time and providing an efficient approach to customization and application development for systems using the CXL 2.0 interface standard.

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Key Takeaways:

  • New VIP supports pre-silicon validation of systems using CXL 2.0 interface standard

  • Supports QEMU open-source software emulation methodology

  • Enables efficient hardware/software verification to accelerate development cycles, reduce debug time, ensure compliance



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Avery Design Systems

Founded in 1999, Avery Design Systems, Inc. enables system and SOC design teams to achieve dramatic functional verification productivity improvements through the use of formal analysis applications for gate-level X-pessimism verification and real X root cause and sequential back tracing; and robust core-through-chip-level Verification IP for PCI Express, CXL, CCIX, Gen-Z, USB, AMBA, UFS, MIPI CSI/DSI, I3C, DDR/LPDDR, HBM, ONFI/Toggle/NOR, NVM Express, SATA, AHCI, SAS, eMMC, SD/SDIO, CAN FD, and FlexRay standards. The company has established numerous Avery Design VIP partner program affiliations with leading IP suppliers. More information is available at www.avery-design.com.

Contacts:

Christopher Browy
(978) 851-3627
cbrowy@avery-design.com

Toni Sottak
(843) 530-4442
toni@wiredislandpr.com

Source: Avery Design Systems

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